This invention relates to a clocked comparator and to a programmable signal generator. More particularly this invention relates to an apparatus and method for a high frequency clocked comparator and to an apparatus for a multi-phase programmable signal generator.
The basic function of a comparator is to examine a pair of signals so as to generate a comparison signal having one of two states depending on which examined signal has the largest value. In a clocked comparator the comparison occurs generally within a single clock cycle of a clock signal. The clock signal in a clocked comparator is generally a high frequency signal. Because signal evaluation typically must be completed in the first half of the clock cycle, the signals to be examined must be stable during the interval of the comparison. In a typical clocked comparator where one of the signals to be examined is fixed and the other signal (hereinafter identified as a data signal) is compared to the fixed signal, the data signal must achieve a "steady-state" condition during the first half of the clock cycle so that the comparison can be made. As such, the "settling time" of the data signal is temporally limited by the duration of the first half of the clock cycle. Alternatively, the clock cycle may be extended so as to accommodate the "setting time" of the data signal within the first half of the extended clock cycle. As such, the typical clocked comparator must operate at a slower frequency. This limitation of the typical comparator circuit is overcome by the present invention. In this Specification the "settling time" of the data signal is defined as the temporal interval required for the data signal to achieve a "steady-state" condition.
A clock generator is generally a device which produces a timing signal within a temporal period bounded by a clock cycle and having a unique wave-form. The wave-form is repeated in subsequent clock cycles. It is desirable to employ a clock generator that is simple so that it can be integrated onto an application specific integrated circuit (ASIC) at low cost. It is also desirable for the clock generator to generate a plurality of timing signals wherein each timing signal is programmable. The present invention provides a multi-phase programmable clock generator that may be implemented on a single ASIC chip.